A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

This paper analyzes the performance requirements that need to be met by a clock generator applied low-temperature quantum computer and negative effects on circuit under conditions. In order meet proposed in this suppress brought about low temperature, for ultra-low-temperature computing is designed. designed using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, other techniques. And noise characteristics of are analyzed Impulse Sensitive Function (ISF) simulation results. After tests, average consumption 7 mW, phase −121 dBc/Hz@1 MHz, jitter 62 fs. The meets paper, reduction corner frequency proves will have better at temperatures.